Semiconductor integrated circuit, ink cartridge having the semiconductor integrated circuit, and inkjet recording device having the ink cartridge attached

ABSTRACT

A delay unit is used to prevent writing errors due to residual charge on a bit line when changing rows to write to another bit line. By having a delay unit, a discharge time for discharging charge stored in a parasitic capacitance is reserved. An address is changed after the elapse of the reserved discharge time to assure that discharge is completed and writing errors do not occur. Charge can quickly build up in signal lines of a semiconductor integrated circuit having a charge unit for charging lines in a memory array of n rows and m columns. Write errors can therefore occur when charging a signal line corresponding to a next row after writing to all bits of one column is completed, and then sequentially writing to each bit in the column corresponding to the signal line charged by the charge unit.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a semiconductor integrated circuit, anink cartridge having the semiconductor integrated circuit, and an inkjetrecording device having the ink-cartridge attached, more particularly toa semiconductor integrated circuit having a non-volatile memory built inand using boosted voltage for data writing, an ink cartridge having thesemiconductor integrated circuit, and an inkjet recording device havingthe ink cartridge attached.

2. Background Art

Conventionally, such a semiconductor integrated circuit performs a writeoperation by voltage boosted by an internal booster circuit when writingdata on a built-in, non-volatile memory. At the end of writing, chargestored in a signal line charged at the time of writing is dischargedbefore shifting to the next writing operation. In this case, thedischarging is performed by a discharge circuit within a semiconductorintegrated circuit.

FIG. 13 is a circuit diagram showing a discharge circuit in aconventional semiconductor integrated circuit. As shown in FIG. 14, thedischarge circuit discharges charge stored in a parasitic capacitance Cxassociated with each signal line of a memory cell array 5. The parasiticcapacitance Cx is charged in the following manner. An address counter 2performs a count operation in response to an input of a write signal WRso that the address decoder 103 operates with the count value fromcounter 2 as input. The address decoder 103 includes a column decoder 4and a row decoder 3 for respectively specifying a column and a row ofmemory cells from among the plurality of rows and columns of memorycells forming the memory cell array 5. The memory cell array 5 includesa plurality of memory cells arranged in n rows by m columns.

Each output of the column decoder 4, that is the decoded result, isinput to the base terminal of a corresponding transistor Tr1, Tr2, . . .and Trm, which are switching elements. Then, a source terminal of eachtransistor is connected to a data line DW while drain terminal isconnected to a signal line corresponding to each column of memory cellsin the memory cell array 5. Therefore, by turning any one of transistorsTr1, Tr2, . . . and Trm to the ON state with the output of the columndecoder 4, a signal line corresponding to each column is charged byvoltage of the data line DW through the transistor. In other words,charge is stored in a parasitic capacitance of the signal linecorresponding to the column specified by the column decoder 4. Forexample, when the transistor Tr1 is turned ON, charge is stored in aparasitic capacitance shown added to a signal line at a node A.

Here, an output of the input/output control circuit 8 is supplied to thedata line DW. The input/output control circuit 8 includes an internalbooster circuit 107 for boosting voltage of a power supply V_(DD) inresponse to an input of the write signal WR, an inverter for generatingan inverted signal of the write signal WR, a switching transistor 106 towhose gate terminal is supplied the output of the inverter 105, which isthe inverted signal of the write signal WR, and a buffer 108 supplyingto data line DW a voltage corresponding to thy data value of input I/O.Buffer 108 receives as a power supply the output V_(pp) of boostercircuit 107.

In the circuit 101 having such a construction, the write signal WR is athigh level when writing to a memory cell while the transistor 106 is inthe OFF condition. Here, the power supply V_(DD) is supplied to theinternal booster circuit 107, resulting in a higher potential (15 volt,for example) for the boosted output V_(PP). The potential is supplied tothe buffer 108 as a power supply. Thus, voltage corresponding to a valueof the data input I/O is supplied from the buffer 108 to the data lineDW. In this condition, turning any one of the transistors Tr1, Tr2, . .. to the ON condition results in a signal line of the correspondingcolumn being charged by the voltage of the data line DW through thetransistor. In the condition where the signal line is charged (thecondition where charge is stored), data is written in each one of memorycells within the memory cell array 5 by the sequential changes in theoutputs of the row decoder 3.

ON the other hand, at the time of reading from a memory cells, and atother times, the write signal WR is at the low level and the transistor106 is turned ON. At this time, the power supply V_(DD) is not suppliedto the internal booster circuit 107, which turns the boosted output VPPto a lower non-boosted potential (5 volt, for example). The buffer 108,which receives the lower, non-boosted potential V_(pp) as its powersupply, responds by bringing its output to the low level regardless ofthe value of the data input I/O. Therefore, the above-described storedcharge are discharged through the data line DW to which the output ofthe buffer 108 is supplied. For example, the charge stored in theparasitic capacitance Cx shown added to node A is discharged towardground through buffer 108.

In short, in the conventional discharge circuit, by turning transistor106 to the ON state at the end of a writing operation, the accumulatedcharge is discharged. However, in the semiconductor integrated circuit101 having such a discharge circuit, there are problems as follows:

First of all, it takes time for removing charge completely. Thus, thereis a problem that a certain amount of time is required before writing tothe next memory cell.

Further, when the count value of the address counter changes at the sametime as the end of a writing operation, residual charge in the parasiticcapacitance resulting in higher voltage than expected, may lead to theerror of wrong writing due to the parasitic capacitance not beingcompletely discharged. The wrong writing will be described withreference to FIG. 14.

In the figure, when writing on a X1 column of memory cells, thetransistor Tr1 is turned ON by the column decoder 4, first of all, andthe parasitic capacitance Cx shown at node A is charged. In the chargedcondition, writing is performed by the row decoder 3 in order from rowY1, to row Y2 . . . to row Yn. When each writing operation is completed,the parasitic capacitance Cx is discharged as described above. After thedischarging following the writing operation to row Yn, the transistorTr2 corresponding to a next column of X2 is turned ON by the columndecoder 4, and a next parasitic capacitance Cx is charged. In thecharged condition, writing is performed by the row decoder 3 in orderfrom row Y1, to row Y2 . . . to row Yn. Charging and discharging isrepeatedly on the remaining signal lines in similar manner. Through thisoperation, each 1 bit is addressed in order from column X1 and row Y1 tocolumn Xm and row Yn, by which writing is performed on all memory cellsof memory cell array 5.

In the operation above, when transitioning from a writing operation oncolumn X1 and row Yn to a writing operation on column X2 and row Y1, itmay happen that row Y1 is selected before the discharging of the signalline of column X1 is fully complete. In this case, there is a problemthe residual charge may cause wrong writing (i.e. writing to the wrongmemory cell).

The present invention was made in order to overcome the problems of theabove-describe conventional technology. A purpose of the presentinvention is to provide a semiconductor integrated circuit having adischarge circuit, that can surely discharge, an ink cartridge using it,and an inkjet recording device having the cartridge.

DISCLOSURE OF INVENTION

In a first aspect of the present invention, a memory addressing circuitsequentially cycles through all memory cells within a memory array whena memory circuit is placed in write mode of operation. Furthermore, atransition suppressing circuit, or delay circuit, inhibits thetransitioning from a first addressed memory cell to the next addressedmemory cell for a predetermined time period following the completion ofa write operation to the first addressed memory cell. In the presentlypreferred embodiment, the program voltage generating circuit, whichselectively supplies a high programming voltage to a memory cell duringa write operation, is also used to discharge a column line following theend of the write operation. The time period used by the transitionsuppressing circuit is selected such that the program voltage generatingcircuit has enough time to fully discharge the column line prior to thenext memory cell being selected. This is especially important whentransitioning from a first column of memory cells to the next column ofmemory cells since the column line corresponding to the first column ofmemory cells remains floating once the next column line is selected.Therefore, any residual charge remaining on the first column line maycause erroneous writing to an unintended memory cell within the firstcolumn when a row line is activated for addressing a memory cell in thenext column.

A semiconductor integrated circuit according to the present inventionincludes a charge means for charging a signal line corresponding to each1 row in response to an input of a writing instruction for each bit of amemory cell arranged in n rows by m columns (where n and m are naturalnumbers and so forth) and charging a signal line corresponding to a nextrow after writing on all bits for one row is completed. Thesemiconductor integrated circuit performs writing on each 1 bitsequentially in each of bits for 1 row corresponding to the signal linecharged by the charge means. Further, the semiconductor integratedcircuit includes a delay means for delaying an input of the writinginstruction to the charge means for at least a time equivalent to adischarge time for the signal line.

Another semiconductor integrated circuit according to the presentinvention includes a charge means for charging a signal linecorresponding to each 1 row in response to an input of a writinginstruction for each bit of a memory cell arranged in n rows by mcolumns and charging a signal line corresponding to a next row afterwriting on all bits for one row is completed. The semiconductorintegrated circuit performs writing on each 1 bit sequentially in eachof bits for 1 row corresponding to the signal line charged by the chargemeans. Further, the semiconductor integrated circuit includes asuppressing means for suppressing a change in address indicating a cellto be written within a predetermined time after completing the writingfor 1 bit. In this case, the suppressing means may be a delay circuitfor delaying an input of the writing instruction to the charge means forat least a time equivalent to a discharge time for the signal line.

Another semiconductor integrated circuit includes a charge means forcharging a signal line corresponding to each 1 row in response to aninput of a writing instruction for each bit of a memory cell arranged inn rows by m columns and charging a signal line corresponding to a nextrow after writing on all bits for one row is completed. Thesemiconductor integrated circuit performing writing on each 1 bitsequentially in each of bits for 1 row corresponding to the signal linecharged by the charge means. Further, the semiconductor integratedcircuit includes a delay means for differentiating timing for completingwriting for 1 bit and timing for changing an address indicating a cellto be written for a time equivalent to a time for charging at least thesignal line.

The above-described charge means comprises a counter for starting ancount operation in response to an input of the writing instruction, acolumn decoder for decoding a count value of the counter, a switchingelement for charging the signal line by connecting a predetermined powersupply to the signal line after turned ON depending on a decode resultby the decoder, and a row decoder for specifying each 1 bit sequentiallyfor 1 row of bits corresponding a signal line charged when the switchingelement is turned ON.

An ink cartridge according to the present invention has theabove-described semiconductor integrated circuit, for storing at least aremained amount of ink on the memory cell.

An inkjet recording device according to the present invention has theabove-described ink cartridge for printing desired image information byusing ink supplied from the ink cartridge.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing one example of a discharge circuitwithin a semiconductor integrated circuit according to the presentinvention.

FIG. 2 is a functional block diagram for describing an internalconstruction of a semiconductor integrated circuit using the dischargecircuit in FIG. 1.

FIG. 3 is a timing chart for describing a read-out operation onto thesemiconductor integration circuit.

FIG. 4 is a timing chart for describing a write-in operation from thesemiconductor integrated circuit.

FIG. 5 is a timing chart showing an operation of each of the parts inFIG. 1.

FIG. 6 is a waveform diagram showing a state of charging/discharging ofa parasitic capacitance.

FIG. 7 is a diagram showing a circuit substrate on which thesemiconductor integrated circuit shown in FIG. 1 is implemented.

FIG. 8 is a diagram showing a condition where the circuit substrateshown in FIG. 7 is implemented on an ink cartridge.

FIG. 9 is a diagram for showing an overview of an inkjet printer towhich the ink cartridge shown in FIG. 8 is attached.

FIG. 10 is a diagram showing a construction of a carriage shown in FIG.9.

FIG. 11 is a diagram for showing a condition before an ink cartridge isattached to a holder.

FIG. 12 is a diagram for showing a condition where an ink cartridge isattached to a holder.

FIG. 13 is a block diagram showing one example of a conventionaldischarge circuit.

FIG. 14 is a diagram for describing an operational example of thedischarge circuit shown in FIG. 13.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, an embodiment of the present invention will be described withreference to drawings. In each of the drawings referenced indescriptions below, parts similar to those in other drawings are similarby identical reference numerals.

FIG. 1 is a circuit diagram showing a construction example of adischarge circuit within a semiconductor integrated circuit according tothe present invention. The discharge circuit shown in the figure isdifferent from a conventional circuit shown in FIG. 13, and a delaycircuit 10 is inserted before an address counter 2. Further, an AND gate109 is provided in place of a buffer 108.

In the circuit in this construction, an input of a write signal WR tothe address counter 2 can be delayed by the delay circuit 10. That is,by delaying the update function of the address counter 2 for selectingthe next address after a writing operation, sufficient time can thus bearranged to fully discharge a column line through a correspondingcolumn-selecting transistor, Tr1-Trm, and AND gate 109. Morespecifically, the discharge is performed through the column-selectingtransistor via the internal output stage of AND gate 109.

In general, in such semiconductor integrated circuits, address updatingmay take place anytime within a response margin following the trailingedge, i.e. transition event, of the right signal WR. However, incircuits having automatically incremented address counters, like. in thepresent circuit, residual charge, as described above, can remain on acolumn line between address update events if the discharge time, i.e.the time between a write signal transition event and an address updateevent, is not made long enough. Therefore, in the present circuit, thetransition event of the write signal WR and the address updating eventsare offset from each other. More specifically, the discharge time isassured predetermined time margin, set by delay circuit 10, by delayingan address update event following a transition event of the write signalWR.

In this case, the discharge speed depends on a driving capability(equivalent resistance) of the discharge circuits, such as AND gate 109and column-select transistors Tr1-Trm, and the delay time can becalculated as the product of an equivalent resistance R and acapacitance Cx, that is, a time constant. Further, in order to reducethe size of the circuit as much as possible, it is convenient to keepthe insertion of the delay circuit 10 at one point. Thus, in thisembodiment, it is provided at a position before the address counter 2(input side).

FIG. 2 is a functional block diagram for describing an internalconstruction of a semiconductor integrated circuit using the dischargecircuit shown in FIG. 1. As shown in the figure, a semiconductorintegrated circuit 1 includes an address counter 2 for performing acount operation, a row decoder 3 and a column decoder 4 for decoding acount value in the address counter 2 in order to create an address, amemory cell array 5 for storing data, a write/read control circuit 6 forcontrolling a latch circuit 7 and a buffer B, not shown, whose operationdepends on whether one is writing-in to or reading-out from the memorycell array 5. The latch circuit 7 controlled by the write/readcontrol□circuit 6 is selectively set to a latch state or a pass throughstate. The semiconductor integrated circuit 1 also includes aninput/output control circuit 8 for controlling inputs and outputs ofdata to the memory cell array 5, AND gates G1 to G3, and a delay circuit10 for delaying write signals. Further, the semiconductor integratedcircuit 1 is provided with external terminals P1 to P6.

The count value of the address counter 2 is initialized to apredetermined value based on an inverted signal of a chip-select inputsignal CS input from the external terminal P1. Further, the addresscounter 2 creates updated address data based on a signal input from theAND gate G1. The created address data is input to the row decoder 3 andthe column decoder 4.

The column decoder 4 selects desired vertical column of memory cells inthe memory cell array 5 based on address data input from the addresscounter 2. Similarly, the row decoder 3 selects desired horizontal rowof memory cells in the memory cell array 5 based on address data inputfrom the address counter 2.

The memory cell array 5 is formed by arranging a plurality of memorycells in grids. Each memory cell is turned to an ON state by a selectsignal from the row decoder 3, while a select signal from the columndecoder 4 enables information stored in the memory cell to be read andwritten. In this case, it is assumed that the memory cell array 5 isformed by non-volatile memory cells.

The write/read control circuit 6 determines whether write-in operationor read-out operation is performed on the memory cell array 5 based oxchip-select control signals CS input from the external terminal P1 andsignals output from an AND gate G2 and G3. The output of the AND gate G2is write signal WR. The latch circuit 7 outputs read data of the memorycell array 5 to an external terminal P6 after keeping it for apredetermined period of time, which is output from the input/outputcontrol circuit 8, based on a control signal from the write/read controlcircuit 6. The latch circuit 7 performs either a latch operation or apass through operation depending on an output of the write/read controlcircuit 6. The latch circuit 7 performs the latch operation when theoutput of the write/read control circuit 6 is at the low level, and thelatch circuit 7 operates the pass through operation when the output ofthe write/read control circuit 6 is at the high level. The latchoperation is an operation for maintaining the output state. The throughoperation is an operation for sending out the input signal as an outputsignal as it is.

The input/output control circuit 8 writes, in the memory cell array 5,data input from the external terminal P6, or conversely, outputs dataread out from the memory cell array to external terminal P6 through thelatch circuit 7. The input/output control circuit 8 is operated by writesignals WR. The write signal WR is input to the address counter 2 afterbeing delayed by the delay circuit 10. The delay time of the delaycircuit 10 is a time substantially equal to a time for dischargingcharge accumulated in the above-described parasitic capacitance Cx.According to the construction above, data writing is performed on thememory cell array 5. The written data is, for example, a remainingamount of ink. By writing the amount of remaining ink, the remainingamount of ink can be always monitored.

The AND gate G1 outputs, to the address counter 2 and the And gate G2and G3, a signal which is a logic AND combination of a chip-selectcontrol signal CS input from the external terminal P1 and a clock inputsignal CK input from the external terminal P2.

The AND gate G2 outputs, to the write/read control circuit 6, a signalwhich is a logic AND combination of an output signal from the AND gateG1 and a write/read input signal W/R from the external terminal P3. Onthe other hand, the AND gate G3 outputs, to the write/read controlcircuit 6, a signal which is a logic AND combination of an output signalfrom the AND gate G1 and an invert signal of the write/read input signalW/R from the external terminal P3.

More specifically, when the input signal from the AND gate G1 is “L”,the outputs of the AND gates G2 and G3 are both “L”. On the other hand,when the input signal from the AND gate G1 is “H”, and a write/readinput signal W/R is “H”, the output of the AND gate G2 is “H” while theoutput of the AND gate G3 is “L”. Conversely, if the write/read inputsignal W/R is “L”, the output of the AND gate G2 is “L” while the ANDgate G3 is “H”. In this way, the AND gates G2 and G3 are arranged not tohave undefined outputs even if the write/read input signal W/R varies.

The external terminal P1 is a terminal for inputting a chip-select inputsignal CS, that is a control signal STB for selecting a specific devicewhen a plurality of devices exist at the same time, for initializing theaddress counter 2, and for shifting the operation mode. That is, theexternal terminal P1 in this embodiment is a terminal used both as acontrol terminal for initializing an address counter and as a controlterminal for an operation mode.

The external terminal P2 is a terminal for inputting a clock inputsignal CK that is a reference for the semiconductor integrated circuit 1to operate. The external terminal P3 is a terminal for inputting awrite/read input signal W/R for specifying an access operation on thememory cell array 5 built in the semiconductor integrated circuit 1.

The external terminals P4 and P5 are input terminals for applyingoperational voltage at a high potential voltage level V_(DD) and at alow potential voltage level V_(SS) for the semiconductor integratedcircuit 1 to operate. The external terminal P6 is an input/outputterminal for inputting data to be actually written in the memory cellarray 5 built in the semiconductor integrated circuit 1 and/or foroutputting data read out from the memory cell array 5.

Next, operations of the semiconductor integrated circuit according tothis embodiment will be described with reference to FIGS. 3 and 4.

FIG. 3 is a timing chart for describing a readout operation on asemiconductor integrated circuit. FIG. 3 shows the chip-select controlsignal CS, the write/read input signals W/R, the clock CLOCK, the countvalues of the address counter 2, and the input/output signals I/O in theexternal terminal P6 in FIG. 2. When the readout is performed on thememory cell array 5, the “L” is applied to the external terminal P1,first of all, to initialize the address counter 2. Next, “H” is appliedto the external terminal P1, and clock pulses for an predeterminedreadout start address is input from the external terminal P2. Duringinputting the clock pulses, “L” is applied for specifying the readout isapplied as a write/read input signal W/R from the external terminal P3.

The address corresponding to data is output in a period when theclock-input signal CK is turned to “L”. During the period when the clockinput signal CK is “H”, the value is maintained since it is latchedwithin the latch circuit 7 in the leading edge. In the trailing edge,the address is incremented, and data for the next address is output fromthe external terminal P6.

FIG. 4 is a timing chart for describing a write operation from thesemiconductor integrated circuit, for example. FIG. 4 shows thechip-select control signals CS, the write/read input signals W/R, theclock CLOCK, the count values of the address counter 2, and theinput/output signals I/O in the external terminal P6. When a write isperformed on the memory cell array 5, “L” is applied to the externalterminal P1 in a condition where the write/read input signal W/R is “L”in order to initialize the address counter 2. Next, “H” is applied tothe external terminal P1, and clock pulses for an intended write startaddress are input from the external terminal P2. Then, while the writeoperation is performed, “H” for specifying the write operation isapplied as the write/read input signal W/R from the external terminalP3.

Next, a process for instructing the semiconductor integrated circuit 1for memory initialization and operation mode shifting will be described.As described above, when “L” is applied to the external terminal P1, theaddress counter 2 is initialized. This is a procedure absolutelyrequired for initialization of the semiconductor integrated circuit 1and some other circuits excluding the memory cell array 5, such as thewrite/read control circuit 6. Here, the external terminal P6 is open(hi-impedance condition).

In addition, when “L” is applied to the external terminal P1, thestand-by signal STB for the operation mode shifting is turned to “L”,and the operation mode of the semiconductor integrated circuit 1 isshifted to the stand-by mode. When the operation mode of thesemiconductor integrated circuit 1 is shifted to the stand-by mode, apart where current steadily flows is terminated, which attempting thereduction of the current consumption. More specifically, a senseamplifier provided within the input/output control circuit 8, forexample, always needs current flow. Therefore, in order to suppresspower consumption in the present circuit, when it is at the stand-bymode, the source voltage to be supplied to the input/output controlcircuit 8 is turned to OFF.

Thus, in this embodiment, when the chip-select input signal CS is “L”,that is, when the external terminal P1 is in an unselected condition,the address counter 2 is initialized and the semiconductor integratedcircuit 1 is shifted to the stand-by mode. Since these instructions arecontrolled by the inputs from the external terminal P1, that is adual-usage terminal, the memory initialization function and the functionfor shifting to the stand-by mode are provided, attempting the reductionof the external terminals. Further, the control terminal for the memoryinitialization and the control terminal for operation mode control arecoupled to one dual-usage terminal, which makes the control easier.

In this case, the functions for the circuit block initialization and theoperation mode shifting may be arranged such that the address counter 2is initialized and the semiconductor integrated circuit 1 is shifted tothe stand-by mode when the logical output between the input from theexternal terminal P1 and the input from the other terminals are theunselect condition.

FIG. 5 is a timing chart showing timing for address changes for writesignals in the conventional circuit and the present circuit,respectively. Referring to the figure, voltage of the data line DW ischanged in synchronous with timing of leading and trailing edges of thewrite signals WR. In this example, 0 volt and 15 volt are repeatedalternately. In the conventional circuit, since the delay circuit 10 isnot provided, a content at an address ADRS1 is changed synchronouslywith the trailing edge of the voltage waveform of the data line DW.Thus, the address is changed before discharge of stored charge in theparasitic capacitance is completed, wrong writing may be performed.

On the other hand, since the delay circuit 10 is provided in the presentcircuit, a content of an address ADRS2 is changed with a small delaywhen compared to the case of the address ADRS1. Here, if the delay timeis defined as a time enough for completing the discharge of chargestored in the parasitic capacitance, the address is changed after thecompletion of the discharge. Therefore, in the present circuit, wrongwriting is avoided. In other words, by suppressing a change in addressfor a predetermined period of time, the wrong writing can be prevented.

In FIG. 6, a charging/discharging waveform in the conventional circuitand a charging/discharging waveform in the present circuit are shown.With respect to the change in the data line DW, charge stored in theparasitic capacitance is discharged slowly in a node A of theconventional circuit, as shown in the figure. Therefore, the address ischanged before the completion of the discharge, and wrong writing mayoccur.

On the other hand, in the present circuit, with respect to the change inthe data line DW, charge stored in the parasitic capacitance aredischarged quickly in a node A′. Therefore, the address is changed afterthe completion of the discharge, and the wrong writing does not occur.

As described above, since a delay circuit is provided in the presentcircuit, the address change is suppressed for a predetermined period oftime. Thus, since a time for discharging charge stored in the parasiticcapacitance can be reserved, and since the address is changed after thedischarge is completed, wrong writing does not occur.

FIGS. 7(a) to 7(e) are diagrams for showing a circuit substrate on whicha semiconductor integrated circuit according to this embodiment isimplemented. As shown in FIG. 7(a), contacts 12 are formed on a surfaceside of a circuit substrate 11. These contacts 12 are connected to theabove-described external terminals P1 to P6. Further, as shown in FIG.7(b), the semiconductor integrated circuit 1 is implemented on the backside of the circuit substrate 11.

As shown in FIG. 7(c), the circuit substrate 11 is in a substantiallyrectangular, plate form. The circuit substrate 11 is provided with anotch portion 11 a and a hole portion 11 b. They are used forpositioning the circuit substrate 11 when implemented on anink-cartridge described below. Further, as shown in FIG. 7(d), a recess12 a may be provided on the surface of each of the contacts 12 providedon the circuit substrate 11. Providing the recess 12 a, as shown in FIG.7(e) improves the electric connection condition with a contact 29provided on the ink cartridge described below.

FIGS. 8(a) and (b) are diagrams for showing a condition where thecircuit substrate shown in FIG. 4 is implemented on an ink cartridge.FIG. 8(a) shows a condition where the circuit substrate 11 isimplemented on a black ink cartridge 20 accommodating black ink. Theblack ink cartridge 20 accommodates, in a container 21 formed as asubstantial rectangular parallelepiped, a porous body, not shown,impregnated with black ink, and the top surface is sealed by a lid body23. On the bottom surface of the container 21, an ink supplying outlet24 is formed at a position facing to an ink supplying needle whenattached to a holder. In addition, an overhang portion 26 associatedwith a projection of a lever of the body is formed integrally at anupper edge of a vertical wall 25 at the side of the ink supplyingoutlet. The overhang portions 26 are formed on the both side of the wall25 separately, and each has a rib 26 a. Further, a rectangular rib 27 isformed between a bottom surface and the wall 25.

The circuit substrate 11 is attached at the side where the ink supplyingoutlet of the horizontal wall 25 is formed. The circuit substrate 11 hasa plurality of contacts on a surface facing to the contacts of the bodyand has a memory element implemented on the back surface. In addition,projections 25 a and 25 b and overhang portions 25 c and 25 d are formedon the horizontal wall 25 in order to position the circuit substrate 11.

On the other hand, FIG. 8(b) shows a condition where the implementedcircuit substrate 11 is implemented on a color ink cartridgeaccommodating color ink. The color ink cartridge 30 accommodates, in acontainer 31 formed as a substantially a rectangular parallelepiped, aporous body, not shown, impregnated with ink and sealed with a lid body33 on the upper surface.

Five ink accommodating portions accommodating five colors of color inkseparately and respectively are sectionally formed inside of thecontainer 51. At the bottom surface of the container 31, an inksupplying outlet 34 is formed depending on each ink color at a positionfacing to an ink supplying needle when attached to the holder. Inaddition, an overhang portion 36 associated with a projection of a leverof the body is formed integrally at an upper edge of a vertical wall 35at the side of the ink supplying outlet. The overhang portions 36 areformed on the both side of the wall 35 separately, and each has a rib36a. Further, a rectangular rib 37 is formed between a bottom surfaceand the wall 35. Furthermore, the container 31 has a recess 39 in orderto prevent the mis-insertion.

A recess 38 is formed at a side of the horizontal wall 35 where an inksupplying outlet is formed such that it is positioned at the center ofeach cartridge 30 in the width direction, and the circuit substrate 11is attached here. The circuit substrate 11 has a plurality of contactson a surface facing to the contacts of the body and has a memory elementimplemented on the back surface. In addition, projections 35 a and 35 band overhang portions 35 c and 35 d are formed on the horizontal wall 35in order to position the circuit substrate 11.

FIG. 9 is a diagram showing an overview of an inkjet printer (inkjetrecording device) to which an ink cartridge shown in FIG. 8 is attached.In FIG. 9, a holder 44 for storing each of the black ink cartridge 30shown in FIG. 8(a) and the color ink cartridge 30 shown in FIG. 8(b) isformed in a carriage 43 connected to a driving motor 42 through a timingbelt 41. Further, a recording head 45 for receiving the supply of inkfrom each of the ink cartridges 20 and 30 at a bottom surface positionon the carriage 43.

Ink supply needles 46 and 47 communicating with a recording head 45 isprovided vertically on the bottom surface of the carriage 43 such thatthey are positioned at the inner part of the device, that is on the sideof the timing belt 41.

FIG. 10 is a diagram showing a construction of the carriage shown inFIG. 9. As shown in FIG. 10, levers 51 and 52 are mounted rotatably withrespect to axes 49 and 50 as fulcrums at the upper edge of a verticalwall 49 closely facing to the ink supply needles 46 and 47 amongvertical walls forming the holder 44.

The wall 53 positioned on the side of free edges of the levers 51 and 52have a slope portion where the bottom surface side is cut diagonally.Further, contact mechanisms 54 and 55 are provided on the vertical wall48. The contact mechanisms 54 and 55 connected to the above-describedcontacts provided on the circuit substrate 11 in a condition where theink-cartridge is attached. Thus, ink cartridge recording can beperformed by using ink within the ink cartridge.

Additionally, a base platform 56 is mounted on the vertical wall 48 ofthe holder 44. Then, a circuit substrate 57 is mounted on the backsurface of the base platform 56. The circuit substrate 57 iselectrically connected with the contact mechanisms 54 and 55, resultingin that the circuit substrate 11 and the circuit substrate 57 providedin the ink cartridge are electrically connected.

FIG. 11 is a diagram showing a condition before the ink cartridge isattached to the holder, while FIGS. 12(a) to (c) are diagrams showingconditions where the ink cartridge is attached to the holder. As shownin FIG. 11, when the lever 51 is closed in a condition where the inkcartridge 20 is inserted to the holder 44, the ink cartridge 20 ispressed gradually in a direction of an arrow Y. Here, a condition shownin FIG. 12(a) is transited to a condition shown in FIG. 12(c), and theink supply needle 46 is inserted inside of the ink cartridge 20. Ink issupplied from the ink cartridge 20 in a condition where the ink supplyneedle 46 is inserted inside of the ink cartridge 20 and the inkcartridge 20 is attached to the holder 44 completely, that is, in acondition shown in FIG. 12(c).

In the condition shown in FIG. 12(c), the contacts 12 provided on thecircuit substrate 11 and the contacts 29 on the circuit substrate 57provided on the side of the holder 44 are electrically connected. Thus,an inkjet printer can read and write data freely to/from thesemiconductor integrated circuit 1. More specifically, when the powersupply of the printer is ON, “L” is applied to the external terminal P1,while “H” is applied when a read or write operation needs to beperformed. It can simplify the logic and contribute to the reduction ofthe chip size.

INDUSTRIAL APPLICABILITY

Thus, in this embodiment, there is an effect that, by defining a delayof timing as a time equal to or more than a time required for chargedischarging, wrong writing due to residual charge can be prevented.

In general, several bits including 8 bits and 16 bits are regarded asone word, and this is often handled as a unit for reading and writing.However, in this case, a buffer is needed for storing one wordtemporally. Thus, the size of a circuit is increased, which is notsuitable for being installed. in an ink cartridge. Therefore, in thepresent circuit, reading and/or writing are performed for every 1 bitafter dividing one word into every 1 bit. Thus, in the present circuit,a buffer is no longer required for maintaining one word, which canreduce the size of a circuit and allows the installation in the inkcartridge.

Furthermore, by storing the remained amount of ink in an ink cartridge,at least, the remained amount of ink cartridge can be always monitored.

What is claimed is:
 1. A semiconductor integrated circuit comprising: aplurality of memory cells arranged in an array of n rows and m columns;a plurality of column signal lines having a one-to-one correspondencewith each of said m columns; a program addressing circuit forsequentially charging each of said column signal lines in response to awriting instruction for writing to all memory cells of said array, saidprogram addressing circuit being effective for charging the next columnsignal line corresponding to the next column of memory cells afterwriting to all memory cells in a current column is complete, saidsemiconductor integrated circuit being effective for sequentiallywriting to each memory cell in the column corresponding to the currentcolumn signal line charged by said program addressing circuit; and adelay circuit for delaying an address transition of said programaddressing circuit for at least a time equivalent to a discharge timefor said column signal lines.
 2. A semiconductor integrated circuitaccording to claim 1, wherein said delay circuit is further effectivefor defining a first time period for completing a writing operation toone memory cell and a second time period for changing the addressindicating the next memory cell to be written following the completionof said writing operation to one memory cell, said second time periodbeing used for said delaying of said address transition of said programaddressing circuit.
 3. A semiconductor integrated circuit according toclaim 1, wherein said program addressing circuit includes: a counter forstarting a count operation in response to said input of said writinginstruction; a column decoder for decoding a count value from saidcounters; a switching element for charging said column signal lines byconnecting a predetermined power supply to said column signal lines inresponse to a decoded result from said column decoder; and a row decoderfor sequentially selecting each row of memory cells corresponding to thecolumn signal line being charged by said switching element.
 4. An inkcartridge having the semiconductor integrated circuit according to claim1, said semiconductor integrated circuit being connected so as to beeffective for storing in said memory array at least the amount ofremaining ink in said ink cartridge.
 5. An inkjet recording devicehaving an ink cartridge according to claim 4 for printing desired imageinformation by using ink supplied from the ink cartridge.
 6. Asemiconductor integrated circuit comprising: a memory array including aplurality of memory cells arranged in n rows and m columns; a write nodefor receiving a write signal, said semiconductor integrated circuitactuating a write operation on said memory array in response to saidwrite signal being at a first logic level and ceasing said writeoperation in response to said write signal being at a second logiclevel; a program voltage transfer circuit having a program voltageoutput node and effective for selectively applying a programming voltageto said program voltage output node during the application of said writeoperation, said programming voltage being sufficient for altering thedata content stored in said memory cells; an address decoder having anaddress input and effective for selecting a target memory cell withinsaid memory array in accordance with said address input, said addressdecoder being further effective for routing said program voltage outputnode to said target memory cell; an address selection circuit forsupplying a new target address to said address input in response to alogic transition of said write signal; and a transition suppressingcircuit for suppressing the application of said new target address tosaid address input for a predetermined time period following said logictransition of said write signal.
 7. The semiconductor integrated circuitof claim 6, wherein said transition suppressing circuit is a delaycircuit responsive to said write node.
 8. The semiconductor integratedcircuit of claim 7, wherein said address selection circuit is an addresscounter.
 9. The semiconductor integrated circuit of claim 8, whereinsaid address counter increments its address count in response to saidlogic transition of said write signal.
 10. The semiconductor integratedcircuit of claim 9, wherein said logic transition of said write signalis a transition from said first logic level to said second logic level.11. The semiconductor integrated circuit of claim 9, wherein said writenode is coupled to said address counter through said delay circuit. 12.The semiconductor integrated circuit of claim 6, further having a datainput node for receiving an input data signal; said program voltagetransfer circuit applying said programing voltage to said programvoltage output node in accordance with said input data signal duringsaid write operation.
 13. The semiconductor integrated circuit of claim12, wherein said program voltage transfer circuit maintains asubstantially ground potential at said program voltage output node whenno write operation is being applied to said memory array.
 14. Thesemiconductor integrated circuit of claim 6, wherein said addressdecoder includes a plurality of transfer circuits for selectivelycoupling said program voltage output node to a targeted one of saidcolumn lines or row lines.
 15. The semiconductor integrated circuit ofclaim 14, further having a write/read input node effective forindicating one of a write mode of operation and a read mode of operationfor said memory cell array, said semiconductor integrated circuitresponding to said write signal only when said write/read input nodeindicates said write mode of operation; said address decoder maintainingsaid program voltage output node coupled to said targeted one of saidcolumn lines or row lines as long as said write/read input nodeindicates said write mode of operation irrespective of the logic levelof said write signal.
 16. The semiconductor integrated circuit of claim6, wherein said address decoder includes a plurality of transfercircuits for selectively coupling said program voltage output node to atargeted one of said column lines, and wherein; said address selectioncircuit is further effective for targeting said memory cells in aspecific sequence pattern, said sequence pattern consisting ofsequentially addressing all memory cells within a first targeted columnof memory cells and upon reaching the last memory cell on said firsttargeted column, selecting an adjacent column of memory cells as asecond targeted column and then sequentially addressing all memory cellswithin said second targeted column, said specific pattern being repeateduntil all memory cells within said memory array are addressed.
 17. Thesemiconductor integrated circuit of claim 6, further having a columnline per column of memory cells for addressing all memory cells coupledto a respective column line, and a row line per row of memory cells foraddressing all memory cells coupled to a respective row line, a targetmemory cell being addressed by selection of its corresponding columnline and row line, and wherein; said predetermined time period issubstantially equal to the time required to discharge one of said columnlines.
 18. An ink cartridge having the semiconductor integrated circuitaccording to claim 6, said semiconductor integrated circuit beingconnected so as to be effective for storing in said memory cell array atleast the amount of remaining ink in said ink cartridge.
 19. An inkjetrecording device having an ink cartridge according to claim 18 forprinting desired image information by using ink supplied from said inkcartridge.